Electronic circuits, and particularly computer and instrumentation circuits, have in recent years become increasingly powerful and fast. As circuit frequencies delve into the gigahertz (GHz) region, with their associated high frequency transients, noise in the DC power and ground lines increasingly becomes a problem. This noise can arise due to inductive and capacitive parasitics, for example, as is well known. To reduce such noise, capacitors known as decoupling capacitors are often used to provide a stable signal or stable supply of power to the circuitry.
Capacitors are further utilized to dampen power overshoot when an electronic device, such as a processor, is powered up, and to dampen power droop when the electronic device begins using power. For example, a processor that begins performing a calculation may rapidly need more current than can be supplied by the on-chip capacitance. In order to provide such capacitance and to dampen the power droop associated with the increased load, off-chip capacitance should be available to respond to the current need within a sufficient amount of time. If insufficient current is available to the processor, or if the response time of the capacitance is too slow, the die voltage may collapse.
Decoupling capacitors and capacitors for dampening power overshoot or droop are generally placed as close to the load as practical to increase the capacitors' effectiveness. Often, these capacitors are surface mounted to the electronic device or the package substrate on which the device is mounted. At increasingly reduced device sizes and packing densities, however, available real estate for surface-mounted capacitors becomes a limiting factor.
One solution has involved the formation of a parallel plate capacitor integrated on or embedded within a substrate. FIG. 1 illustrates a parallel plate capacitor 102 in accordance with the prior art. Capacitor 102 includes two planar conductors 104. When separated by a non-conducting material (not shown), a charge can be stored across the capacitor 102.
FIG. 2 illustrates a cross section of an embedded parallel plate capacitor coupled to a die 204 in accordance with the prior art. The embedded capacitor includes two planar conductors 206, 208 that are separated by a thin dielectric layer 210 (e.g., 1 micron or less). The dielectric material used in layer 210 must have a high dielectric constant in order to provide the amount of capacitance needed. To have a capacitance large enough for the decoupling of CPUs, this dielectric constant has a value in the thousands (e.g., within a range of 2000 to 5000) or many layers must be stacked. Desirably, the planar conductors 206, 208 are located below the die 204, in order to be close to any die load that may require capacitance, or to effectively reduce noise in the DC power and ground lines supplied to the die.
One of the two planar conductors 206 or 208 is connected, via conductive paths 212, to ground terminals of one or more die loads (not shown). The other planar conductor 208 or 206 is connected, via conductive paths 212, to power terminals of the one or more die loads. These planar conductors 206, 208, coupled with the thin dielectric layer 210, provide capacitance for noise, power overshoot, and power droop dampening, as modeled by capacitor 216.
FIG. 3 illustrates an electrical circuit that simulates the electrical characteristics of the parallel plate capacitor illustrated in FIG. 2. The circuit shows a die load 302, which may require capacitance or noise dampening in order to function properly. Some of the capacitance can be supplied by capacitance 304 located on the die. Other capacitance, however, must be provided off chip, as indicated by off-chip capacitor 306. The off-chip capacitor 306 could be, for example, the embedded parallel plate capacitor illustrated in FIG. 2. The off-chip capacitor 306 may more accurately be modeled as a capacitor in series with some resistance and inductance. For ease of illustration, however, off-chip capacitance 306 is modeled as a simple capacitor.
Naturally, the off-chip capacitor 306 would be located some distance, however small, from the die load 302, due to manufacturing constraints. Accordingly, some inductance 308 exists between the die load and the off-chip capacitance. Because the inductance 308 tends to slow the response time of the off-chip capacitor 306, it is desirable to minimize the distance between the off-chip capacitance 306 and the die load 302, thus reducing the inductance value 308. This can be achieved by placing the off-chip capacitor 306 as close as possible to the die load.
In order to increase the amount of capacitance supplied by the parallel plate capacitor, the surface area of the plates can be increased. Increasing the surface area, however, increases the risk of shorts or leakage between the plates, thus reducing yield and increasing reliability concerns.
Besides reliability concerns, the parallel plate capacitor solution may not be sufficient for many higher frequency applications. This is because the parallel plate capacitance is spread out over a large area, resulting in large lateral parasitics that may prevent the timely flow of charge to “hot spots” on the die (i.e., localized portions of the die that require large amounts of current in short periods of time). In addition, the propagation of the charge is a strong function of not only inductance, but also capacitance. Therefore, the lateral parasitics and relatively high capacitance characteristic of an embedded parallel plate capacitor may unacceptably slow the charge response time to the die hot spots, resulting in a collapse of the die voltage supply.
As electronic devices continue to advance, there is an increasing need for higher levels of capacitance at reduced inductance levels for decoupling, power dampening, and supplying charge. Accordingly, there is a need in the art for alternative capacitance solutions in the fabrication and operation of electronic and integrated circuit devices.